MSU-IIT, DOST-PCIEERD, and Singapore’s Synopsys train Mindanao universities on IC Design

by (contributed news) | Sep 02 2019

To strengthen IC and system design awareness in the academe, the Institute, through the Microelectronics Laboratory of the Department of Electrical Engineering and Technology (DEET) of the College of Engineering and Technology (COET), in coordination with the Office of the Vice Chancellor for Research and Extension, together with the Department of Science and Technology-– Philippine Council for Industry, Energy, and Emerging Technology Research and Development (DOST-PCIEERD), and Singapore’s Synopsys train faculty members of Mindanao universities on IC design.

The colleges and universities which participated in the series of training are Ateneo de Davao University, Holy Cross of Davao College, University of Mindanao, Caraga State University, Surigao State College of Technology, Notre Dame of Marbel University, Notre Dame of Midsayap College, Universidad de Zamboanga, Xavier University – Ateneo de Cagayan, University of Science and Technology of Southern Philippines, MSU – General Santos, MSU – Marawi, and MSU-IIT.

According to the report by Engr. Rochelle M. Sabarillo, senior science research specialist of a DOST - PCIEERD project (uC-IC: Design of Microcontroller Integrated with Energy Harvesting and Power Management), Synopsys, the American company that owns and develops the current IC design tool used by the Institute, provided the training’s resource materials including lecture videos, online laboratory exercises, and soft-bound copies of the workshop laboratory guide.

The series of training featured lectures and laboratory exercises on Cloud-Based Synthesis using Design Compiler, providing the participants a clear understanding of the ASIC flow, as well as increase their skills in ASIC design;  IC Compiler Block Level Implementation, which focuses on using the IC compiler to perform placement, clock tree synthesis (CTS), routing, and design-for-manufacturability (DFM) on block-level designs with an existing floorplan; and on the SoC Design Planning Integration, which was conducted exclusively to DEET faculty members and researchers of the µC-IC project.

According to Sabarillo, the third training was to guide the participants on how to perform multi-voltage hierarchical design planning with a mix of black box and synthesized sub-modules, some of which are multiply-instantiated modules (MIMs) and to help them create a multi-voltage power network using Template-based Power Network Synthesis (TPNS) and use Data Flow Analysis (DFA).

Engr. Nicholas Yee Wee Han, a Senior Applications Engineer of Synopsys based in Singapore, conducted the lectures which were followed by laboratory exercises.

During the training, COET’s Prof. Jefferson Hora and Mr. Alvin Chua Yee Meng, Synopsys Marketing representative, underscored the significance of including microelectronics as a specialized field in the academe and how it can contribute to the country’s economic success.

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